1 master 2-layer metal sla4028 sla4046 sla4078 sla4115 sla4162 sla4239 sla4318 sla4411 features 3-layer metal sla402t sla404t sla407t sla411t SLA416T sla423t sla431t sla441t total bcs (raw gates) 28,260 46,864 78,600 115,388 162,864 239,468 318,308 411,257 usable bcs 2-layer metal 14,130 22,026 35,370 51,924 70,031 95,787 127,323 164,502 3-layer metal 24,868 39,834 62,880 86,541 122,148 167,627 222,815 287,879 number of pads 116 144 184 216 256 308 352 400 (in case of micro pitch) (128) (164) (212) (256) (304) (368) (424) (480) propagation internal gates tpd = 0.160ns (standard at 3.3v) delay input gates tpd = 0.400ns (standard at 5.0v) level shifter, tpd = 0.420ns (standard at 3.3v) output buffers tpd = 1.99ns (standard at 5.0v) level shifter, tpd = 1.89ns (standard at 3.3v) cl = 50pf i/o level cmos, ttl, pci, usb*, lvds* input mode lvttl, ttl, cmos, pull-up/pull-down, schmitt, 2.0/3.0/3.3/5.0v level interface (level shifter) output mode normal, open drain, 3-state, bi-directional, 2.0/3.0/3.3/5.0v level interface (level shifter) * under development pf842-02 sla40000 series n overview the sla 40000 series are super-high-density/speed, sea-of-gate type cmos gate arrays adopting the 0.45 m process. they consume less electricity, a feature of asics dedicated to 3.3v, while enabling high-speed-operation as well as 3v/5v full swing i/f in the level shifter. there are 2- and 3-metal layer for each of 8 models from 28,260 to 411,257 gates, satisfying customer needs for a wide range of circuit size. in addition, the series can be used with various i/f devices such as low noise output cells, pci i/f revision 2.0, gtl i/f*, jtag*, fail/safe output* and test control input*, and have diverse applications such as small information instrument and for image processing. to develop high-speed/high-density circuits in a shorter period of time, the series enable diverse design techniques to be used during development such as high accuracy simulation of interconnection resistance and blunted waveform in addition to the conventional interconnection capacity components, and provide a new layout tool for reducing clock skew. n features l super-high density (adopting 0.45 m m silicon gate cmos with 2- and 3-metal layers) l high-speed operation (operation delay of internal gate = 0.160ns at 3.3v, 2-input power nand standard) l internal gate = 3.3 and 3.0v (2.0v single), i/o buffer = 5.0, 3.3 and 3.0v (2.0v single) (built-in level shifter) l low power consumption (0.80 m w/mhz/bc when internal cell = 3.0v) l output drivability (i ol = 100 m , 1, 3, 6, 12, 24 ma when pci = 5.0v, i ol = 100 m , 1, 2, 6, 12ma when pci = 3.3v, i ol = 50 m , 300 m , 600 m , 2, 4ma when 2.0v) l ram, pll, irda*, and various function cells available l low noise output cell, pci i/f, usb i/f*, lvds*, jtag n product lineup l super-high-density/speed gate array l operates on 3.3 and 3.0v power source (level shifter is pre-installed) l raw of gates: 28 to 411k gates (sea of gates) high density gate array free datasheet http:///
2 sla40000 series electronic devices marketing division electronic device marketing department ic marketing & engineering group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5816 fax: +81-(0)42-587-5624 ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5812 fax: +81-(0)42-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5814 fax: +81-(0)42-587-5110 notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liabilit y of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circu it and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, med ical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic pr oducts under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. all product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ?seiko epson corporation 1998 all rights reserved. http://www.epson.co.jp electric device information of epson www server
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